Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
10-13
10.3.1.4
INTC End-of-Interrupt Register (INTC_EOIR)
Writing to the INTC_EOIR signals the end of the servicing of the interrupt request. When the INTC_EOIR
is written, the priority last pushed on the LIFO is popped into INTC_CPR. The values and size of data
written to the INTC_EOIR are ignored. Those values and sizes written to this register neither update the
INTC_EOIR contents or affect whether the LIFO pops. For possible future compatibility, write four bytes
of all 0’s to the INTC_EOIR.
Reading the INTC_EOIR has no effect on the LIFO.
10.3.1.5
INTC Software Set/Clear Interrupt Registers (INTC_SSCIR0–7)
The INTC_SSCIR
n
support the setting or clearing of software settable interrupt requests. These registers
contain eight independent sets of bits to set and clear a corresponding flag bit by software. With the
exception of being set by software, this flag bit behaves the same as a flag bit set within a peripheral. This
flag bit generates an interrupt request within the INTC just like a peripheral interrupt request. Writing a 1
to SET
n
leaves SET
n
unchanged at 0 but sets CLR
n
. Writing a 0 to SET
n
has no effect. CLR
n
is the flag
bit. Writing a 1 to CLR
n
clears it. Writing a 0 to CLR
n
has no effect. If a 1 is written to a pair SET
n
and
CLR
n
bits at the same time, CLR
n
is asserted, regardless of whether CLR
n
was asserted before the write.
Although INTC_SSCI
n
is 8 bits wide, it can be accessed with a single 16-bit or 32-bit access, provided
that the access does not cross a 32-bit boundary.
21–29
or
20–28
INTVEC
Interrupt vector. Vector of peripheral or software-settable interrupt requests that caused the interrupt request to the
processor. When the interrupt request to the processor asserts, the INTVEC is updated, whether the INTC is in
software or hardware vector mode.
Note:
If INTC_MCR[VTES] = 1, then the INTVEC field is shifted left one position to bits 20–28. VTBA is then
shortened by one bit to bits 0–19.
30–31 or
29–31
Reserved, must be cleared.
Address: Base + 0x0018 (INTC_EOIR)
Access: W/O
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
EOIR
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 10-11. INTC End-of-Interrupt Register (INTC_EOIR)
Address: Base +
n
(INTC_SSCIR
n
);
n
= 0–7
Access: R/W
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
CLR
n
W
SET
n
Reset
0
0
0
0
0
0
0
0
Figure 10-12. INTC Software Set/Clear Interrupt Register (INTC_SSCIR
n
)
Table 10-6. INTC_IACKR Field Descriptions (continued)
Field
Description
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
