NXP Semiconductors MPC5566, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-45
18.4.6.4 eTPU Channel n Host Service Request Register (ETPU_C n HSRR)
ETPU_C n HSRR is used by the device core to issue service requests to the channel.
9
DTROS
Data transfer request overflow status.
0 Data transfer request overflow negated for this channel.
1 Data transfer request overflow asserted for this channel.
DTROS is mirrored in the ETPU_CDTROSR. Refer to
Section 18.4.5.4, “eTPU Channel Data Transfer Request
Overflow Status Register (ETPU_CDTROSR) ” and the eTPU Reference Manual for more information on
ETPU_CDTROSR and data transfer overflows.
The core must write 1 to clear DTROS.
10–15 Reserved
16
IPS
Channel input pin state. Shows the current value of the filtered channel input signal state
17
OPS
Channel output pin state. Shows the current value driven in the channel output signal, including the effect of the
external output disable feature. If the channel input and output signals are connected to the same pad, OPS reflects
the value driven to the pad. This is not necessarily the actual pad value, which drives the value in the IPS bit.
18–29 Reserved
30–31
FM
[0:1]
Channel function mode.
1
Each function can use this field for specific configuration. These bits can be tested by
microengine code.
1
These bits are equivalent to the TPU/TPU2/TPU3 host sequence (HSQ) bits.
Address: Channel_Registe 0x0008 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0
HSR
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 18-24. eTPU Channel n Host Service Request Register (ETPU_CnHSRR)
Table 18-26. ETPU_C n SCR Field Descriptions (continued)
Field Description