NXP Semiconductors MPC5566, Reference Manual

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System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-12 Freescale Semiconductor
The WKPCFG bit retains the latest value of the WKPCFG signal before reset. The BOOTCFG field retains
the latest values of the BOOTCFG[0:1] signals before reset.
Figure 6-3. Reset Status Register (SIU_RSR)
The following table lists and describes the fields of the reset status register:
Address: Base + 0x000C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R PORS ERS LLRS LCRS WDRS CRS 0 0 0 0 0 0 0 0 SSRS
SERF
W
Reset
1
1
The reset status register receives the reset values during power-on reset.
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R WKP
CFG
2
2
The reset value of the WKPCFG bit is the value on the WKPCFG pin at the time of the last reset.
0 0 0 0 0 0 0 0 0 0 0 0 BOOTCFG
RGF
W
Reset
1
U
2
0 0 0 0 0 0 0 0 0 0 0 0 U
3
3
The reset value of the BOOTCFG bits is the value on the BOOTCFG[0:1] pins at he time of the last reset.
0
Table 6-8. SIU_RSR Field Descriptions
Field Description
0
PORS
Power-on reset status.
0 Another reset source was acknowledged by the reset controller since the last assertion of the power-on reset
input.
1 The power-on reset input to the reset controller was asserted and no other reset source was acknowledged
since the assertion of the power-on reset input except an external reset.
1
ERS
External reset status.
0 The last reset source acknowledged by the reset controller was
not a valid assertion of the RESET pin.
1 The last reset source acknowledged by the reset controller was a valid assertion of the RESET pin.
2
LLRS
Loss-of-lock reset status.
0 The last reset source acknowledged by the reset controller was
not a loss-of-PLL lock reset.
1 The last reset source acknowledged by the reset controller was a loss-of-PLL lock reset.
3
LCRS
Loss-of-clock reset status.
0 The last reset source acknowledged by the reset controller was not a loss-of-clock reset.
1 The last reset source acknowledged by the reset controller was a loss-of-clock reset.
4
WDRS
Watchdog timer/debug reset status.
0 The last reset source acknowledged by the reset controller was not a watchdog timer or debug reset.
1 The last reset source acknowledged by the reset controller was a watchdog timer or debug reset.