NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Register Map
MPC5566 Microcontroller Reference Manual, Rev. 2
A-30 Freescale Semiconductor
Reserved — — Base + (0x04CC–0x04CF)
eTPU A channel 13 configuration register ETPU_C13CR_A 32-bit Base + 0x04D0
eTPU A channel 13 status and control register ETPU_C13SCR_A 32-bit Base + 0x04D4
eTPU A channel 13 host service request register ETPU_C13HSRR_A 32-bit Base + 0x04D8
Reserved — — Base + (0x04DC–0x04DF)
eTPU A channel 14 configuration register ETPU_C14CR_A 32-bit Base + 0x04E0
eTPU A channel 14 status and control register ETPU_C14SCR_A 32-bit Base + 0x04E4
eTPU A channel 14 host service request register ETPU_C14HSRR_A 32-bit Base + 0x04E8
Reserved — — Base + (0x04EC–0x04EF)
eTPU A channel 15 configuration register ETPU_C15CR_A 32-bit Base + 0x04F0
eTPU A channel 15 status and control register ETPU_C15SCR_A 32-bit Base + 0x04F4
eTPU A channel 15 host service request register ETPU_C15HSRR_A 32-bit Base + 0x04F8
Reserved — — Base + (0x04FC–0x04FF)
eTPU A channel 16 configuration register ETPU_C16CR_A 32-bit Base + 0x0500
eTPU A channel 16 status and control register ETPU_C16SCR_A 32-bit Base + 0x0504
eTPU A channel 16 host service request register ETPU_C16HSRR_A 32-bit Base + 0x0508
Reserved — — Base + (0x050C–0x050F)
eTPU A channel 17 configuration register ETPU_C17CR_A 32-bit Base + 0x0510
eTPU A channel 17 status and control register ETPU_C17SCR_A 32-bit Base + 0x0514
eTPU A channel 17 host service request register ETPU_C17HSRR_A 32-bit Base + 0x0518
Reserved — — Base + (0x051C–0x051F)
eTPU A channel 18 configuration register ETPU_C18CR_A 32-bit Base + 0x0520
eTPU A channel 18 status and control register ETPU_C18SCR_A 32-bit Base + 0x0524
eTPU A channel 18 host service request register ETPU_C18HSRR_A 32-bit Base + 0x0528
Reserved — — Base + (0x052C–0x052F)
eTPU A channel 19 configuration register ETPU_C19CR_A 32-bit Base + 0x0530
eTPU A channel 19 status and control register ETPU_C19SCR_A 32-bit Base + 0x0534
eTPU A channel 19 host service request register ETPU_C19HSRR_A 32-bit Base + 0x0538
Reserved — — Base + (0x053C–0x053F)
eTPU A channel 20 configuration register ETPU_C20CR_A 32-bit Base + 0x0540
eTPU A channel 20 status and control register ETPU_C20SCR_A 32-bit Base + 0x0544
eTPU A channel 20 host service request register ETPU_C20HSRR_A 32-bit Base + 0x0548
Table A-2. MPC5566 Detailed Register Map (continued)
Register Description Register Name
Used
Size
Address