NXP Semiconductors MPC5566, Reference Manual

Page: 73 / 1268

Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
1-16 Freescale Semiconductor
The flash memory has a flash bus interface unit (FBIU) that connects the system bus to a dedicated flash
memory array controller. The FBIU supports a 64-bit data bus width at the system bus port, and a 256-bit
read data interface to flash memory. The FBIU contains two 256-bit prefetch buffers, and a prefetch
controller that prefetches sequential lines of data from the flash array into the buffer. Prefetch buffer hits
allow no-wait responses. Normal flash array accesses are registered in the FBIU and are forwarded to the
system bus on the following cycle, incurring three wait-states. Prefetch operations can be automatically
controlled, as well as restricted to servicing a single bus master. Prefetches can also require a trigger for
instruction or data accesses.
1.5.10 Cache
The e200z6 core uses the following unified (instruction and data) cache with a 32-byte line size:32-KB,
four- or eight-way set-associative
The cache improves system performance by providing low-latency data to the e200z6 instruction and data
pipelines, which decouples processor performance from system memory performance. The cache is
virtually indexed and physically tagged. The e200z6 does not provide hardware support for cache
coherency in a multi-master environment. Software must be designed to maintain cache coherency with
other possible bus masters.
Both instruction and data accesses are performed using a single bus connected to the cache. The processor
uses virtual addresses to index the cache array. The memory management unit (MMU) provides the
virtual-to-physical address conversion to perform the cache tag compare. The MMU can pass the virtual
addresses to the cache as the physical address without the conversion. If the physical address matches a
valid cache tag entry, the access hits in the cache. For a read operation, the cache supplies the data to the
processor, and for a write operation, the data from the processor is written to cache. If the access does not
match a valid cache tag entry (misses in the cache), or a write access is required to memory, the cache
performs a bus cycle on the system bus.
1.5.11 Static RAM (SRAM)
The MPC5500 family internal SRAM module provides a general-purpose memory block that supports
mapped read/write accesses from any master. The SRAM size is 128 KB. Included within the SRAM block
is a 32-KB block powered by a separate supply for standby operation and ECC error correction and
detection.
1.5.12 Boot Assist Module (BAM)
The boot assist module (BAM) is read-only memory programmed by Freescale and is identical for all
MCUs with an e200z6 core. The BAM program executes every time the MCU is powered on, or when
reset in normal mode. The BAM supports these boot modes:
• Booting from internal flash memory
• Single master booting from external memory
• Serial boot loading (program is downloaded to SRAM over an eSCI or FlexCAN peripheral and
then executed)