NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-75
In single-scan modes, command transfers from the corresponding CFIFO cease when the eQADC
completes the transfer of a entry with an asserted EOQ. Software involvement is required to rearm the
CFIFO so that it can detect new trigger events.
NOTE
An asserted EOQF n only implies that the eQADC has finished transferring
a command with an asserted EOQ bit from CFIFO n . It does not imply that
result data for the current command and for all previously transferred
commands has been returned to the appropriate RFIFO.
19.4.3.6.3 Pause Status
In edge trigger mode, when the eQADC completes the transfer of a CFIFO entry with an asserted pause
bit, the eQADC stops future command transfers from the CFIFO and sets EQADC_FISRn[PF]. The
eQADC ignores the pause bit in command messages in any software level trigger mode. The eQADC sets
the PF flag only in single or continuous-scan edge trigger mode when the pause bit set. When the PF flag
is set for a CFIFO in single-scan edge trigger mode, the EQADC_FISRn[SSS] bit is not cleared.
Refer to the following sections for more information:
Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ”
Section 19.3.2.8, “eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISRn) ”
Section 19.4.1.2, “Message Format in eQADC ,” for information on command message formats.
In level trigger mode, the PF flag designates that a CFIFO n is in the TRIGGERED status. The PF n bit is
set when a closed gate is detected, triggering the CFIFO status change. The pause flag interrupt routine
can be used to verify if a complete scan of the command queue was performed. If a closed gate is detected
while no command transfers are taking place, it has an immediate effect on the CFIFO status. If a closed
gate is detected during the serial transmission of a command to the external device, it has no effect on the
CFIFO status until the transmission completes.
When EQADC_CFCR[PIE] and EQADC_FISRn[PF] are asserted, the eQADC generates a pause
interrupt request. Refer to
Section 19.3.2.6, “eQADC CFIFO Control Registers 0–5 (EQADC_CFCRn) ”
for more information.
NOTE
In edge-trigger mode, an asserted PF n only implies that the eQADC finished
transferring a command with an asserted pause bit from CFIFO n . It does not
imply that result data for the current command and for all previously
transferred commands has been returned to the RFIFO.
NOTE
In software or level trigger mode, when the eQADC completes the transfer
of an entry from CFIFO
n with an asserted pause bit, PF n is not set and the
command transfers continues without pausing.