NXP Semiconductors MPC5566, Reference Manual

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Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
10-4 Freescale Semiconductor
• If the total number of available interrupts is a multiple of four, no additional interrupt vectors exist.
In hardware vector mode, the core branches to an interrupt exception handler unique for each interrupt
request source. Typical program flow for hardware vector mode is shown in
Figure 10-4 .
Figure 10-4. Program Flow–Hardware Vector Mode
For high priority interrupt requests in these target applications, the time from the assertion of the interrupt
request from the peripheral to when the processor is performing useful work to service the interrupt request
needs to be minimized. The INTC can be optimized to support this goal through the hardware vector mode,
where a unique vector is provided for each interrupt request source. It also provides 16 priorities so that
lower priority ISRs do not delay the execution of higher priority ISRs. Since each individual application
has different priorities for each source of interrupt request, the priority of each interrupt request is
configurable.
When multiple tasks share a resource, coherent accesses to that resource need to be supported. The INTC
supports the priority ceiling protocol for coherent accesses. By providing a modifiable priority mask, the
priority level can be raised temporarily so that no task can preempt another task that shares the same
resource.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests,
i.e., by using application software to assert an interrupt request. These same software settable interrupt
requests also can be used to break the work involved in servicing an interrupt request into a high priority
portion and a low priority portion. The high priority portion is initiated by a peripheral interrupt request,
but then the ISR can assert a software settable interrupt request to finish the servicing in a lower priority
ISR.
10.1.3 Features
Features include the following:
• Total number of interrupt vectors is 332
1
, of which:
— 298 are peripheral interrupt vectors
— 8 are software settable sources
Prolog b handler 0 handler 0
ISR
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ISR
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Instructions
NOTE:
‘b ISR_n’ is technically
Epilog
Prolog
Epilog
ISR
Prolog
Epilog
handler n
handler N
b handler 1
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b handler 2
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b handler n
b handler N
IVPR + 0x0000
IVPR + 0x0010
IVPR + 0x0020
IVPR + n [0x0010]
Refer to definition of N
IRQ[n]
taken
Address
part of the handler.