NXP Semiconductors MPC5566, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-22 Freescale Semiconductor
9.2.2.15 DMA Hardware Request Status (EDMA_HRSH, EDMA_HRSL)
The EDMA_HRSH and EDMA_HRSL registers provide a bit map for the implemented channels (16,32,
and 64) to show the current hardware request status for each channel. EDMA_HRSH supports channels
63–32, while EDMA_HRSL supports channels 31–00.
Figure 9-20. EDMA Hardware Request Status Register High (EDMA_HRSH)
Figure 9-21. EDMA Hardware Request Status Register Low (EDMA_HRSL)
Address: Base + 0x0030 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R HRS
63
HRS
62
HRS
61
HRS
60
HRS
59
HRS
58
HRS
57
HRS
56
HRS
55
HRS
54
HRS
53
HRS
52
HRS
51
HRS
50
HRS
49
HRS
48
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R HRS
47
HRS
46
HRS
45
HRS
44
HRS
43
HRS
42
HRS
41
HRS
40
HRS
39
HRS
38
HRS
37
HRS
36
HRS
35
HRS
34
HRS
33
HRS
32
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Address: Base + 0x0034 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R HRS
31
HRS
30
HRS
29
HRS
28
HRS
27
HRS
26
HRS
25
HRS
24
HRS
23
HRS
22
HRS
21
HRS
20
HRS
19
HRS
18
HRS
17
HRS
16
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R HRS
15
HRS
14
HRS
13
HRS
12
HRS
11
HRS
10
HRS
09
HRS
08
HRS
07
HRS
06
HRS
05
HRS
04
HRS
03
HRS
02
HRS
01
HRS
00
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 9-16. EDMA_HRSH and EDMA_HRSL Field Descriptions
Field Description
0–63
HRSn
DMA Hardware Request Status
0 A hardware service request for channel n is not present.
1 A hardware service request for channel n is present.
Note: The hardware request status reflects the state of the request as seen by the arbitration logic.
Therefore, this status is affected by the EDMA_ERQRL[ERQn] bit.