Calibration
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor
B-5
The drive strength of the calibration pins is configured in the PCR registers. In some cases, multiple pads
have their drive strengths controlled by one PCR by grouping the pins:
•
CAL_ADDR[12:30]
•
CAL_DATA[0:15]
•
CAL_RD_WR, CAL_WE/BE[0:1], CAL_OE, CAL_TS
The SIU_PCR registers control whether the CAL_CS[2:3] pins are used for CAL_CS[2:3] or for
CAL_ADDR[10:11]. Refer to
for the pin assignments. Selecting between CAL_CS[2:3] and
CAL_ADDR[10:11] allows you to maximize the amount of calibration memory size by limiting the
number of calibration chip selects to CS[0]. Refer to
Section B.4.1.1, “Number of Chip Selects and
B.4.3
CLKOUT
CLKOUT is supplied by the clock control block, not the EBI. Nevertheless, the same CLKOUT is used
for both the non-calibration and calibration bus.
A drawback of having just one CLKOUT is that while the difference in board timing can be compensated
by the adjustment in the drive strength, the CLKOUT timing, and hence the timing of the non-calibration
bus, can have minor differences with a calibration tool from the production package.
B.5
Packaging
The addition of the calibration bus means that the device has more pads than can be connected to the balls
on a 416 pin package. Therefore, the die is assembled in a 496 pin chip scale package (CSP) and this
package is used in the VertiCal base assembly.
B.6
Power Supplies
The signals that make up the calibration bus have their own power supply segment (V
DDE12
). The V
DDE12
power supply balls are not connected to any other power supply segment from the standard package
ball-out but are routed on the VertiCal base to pins on the VertiCal connector. The VertiCal top board must
provide voltage to the V
DDE12
power supply pins to power up the calibration bus.
B.7
Integration Logic Functionality
The EBI connects to both the non-calibration and calibration buses. The integration logic on MPC5566
selects between the data input from both buses to the EBI.
The MPC5566 integration logic also suppresses the reflections of the outputs of the calibration bus onto
the non-calibration bus. For the non-calibration bus pins that do not have a negated state to which the pins
return at the end of the access, this reflection suppression is enabled by the SIU_CCR[CRSE] bit.
SIU_CCR[CRSE] does not enable reflection suppression for the non-calibration bus pins that have a
negated state to which the pins return at the end of an access. Those reflections always are suppressed.
Furthermore, the suppression of reflections from the non-calibration bus onto the calibration bus is not
enabled by CRSE. Those reflections are also always suppressed.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
