NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 19-3
A CFIFO underflow occurs when a CFIFO:
• Is in the TRIGGERED state; and
• Becomes empty.
An RFIFO overflow occurs when an RFIFO:
• Becomes full; and
• Host CPU or eDMA data is waiting to transmit to the RFIFO.
The eQADC generates eDMA or interrupt requests to control data movement between the FIFOs and the
system memory, which is external to the eQADC.
The eQADC consists of the FIFO control unit which controls the CFIFOs and the RFIFOs, two ADCs with
control logic, and the eQADC synchronous serial interface
(eQADC SSI) which allows communication
with an external device. There are six CFIFOs and six RFIFOs, each with four entries.
The FIFO control unit performs the following functions:
• Prioritizes the CFIFOs to determine which CFIFOs transfer commands
• Supports software and hardware triggers to start command transfers from a particular CFIFO
• Decodes command data from the CFIFOs and sends the commands to one of the two on-chip ADCs
or to the external device
• Decodes result data from on-chip ADCs or from the external device, and transfers data to the
RFIFO
The ADC control logic manages the execution of commands bound for on-chip ADCs from the CFIFOs
and with the RFIFOs via the result format and calibration submodule. The ADC control logic performs the
following functions:
• Buffers command data for execution
• Decodes command data and accordingly generates control signals for the two on-chip ADCs
• Formats and calibrates conversion result data coming from the on-chip ADCs
• Generates the internal multiplexer control signals and the select signals used by the external
multiplexers
The eQADC SSI allows for a full duplex, synchronous, serial communication between the eQADC and an
external device.
Figure 19-1 also depicts data flow through the eQADC. Commands are contained in system memory in a
user-defined queue data structure. Command data is moved from the user-defined command queue to the
CFIFOs by either the host CPU or by the eDMA. After a CFIFO is triggered and becomes the highest
priority, CFIFO command data is transferred from the CFIFO to the on chip ADCs, or to the external
device. The ADC executes the command, and the result is moved through the result format and calibration
submodule and to the RFIFO. The RFIFO target is specified by a field in the command that initiated the
conversion. Data from the external device bypasses the result format and calibration submodule and is
moved directly to its specified RFIFO. When data is stored in an RFIFO, data is moved from the RFIFO
by the host CPU or by the eDMA to a data structure in system memory depicted in
Figure 19-1 as a
user-defined result queue.