NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-1
Chapter 1
Introduction
1.1 Overview
The MPC5566 microcontroller (MCU) is a member of the MPC5500 family of next generation powertrain
microcontrollers built on Power Architecture
™
technology. The MPC5500 family contains a host
processor core that complies with the Power Architecture embedded category, which is 100 percent user
mode compatible with the original Power PC
™
user instruction set architecture (UISA). This family of
parts contains many new features coupled with high-performance CMOS technology to provide significant
performance improvement over the MPC565.
The e200z6 CPU of the MPC5500 family is part of the family of CPU cores that implement versions built
on the Power Architecture embedded category. This core also has additional instructions, including digital
signal processing (DSP) instructions, beyond the classic PowerPC instruction set.
The MPC5566 has the following memory hierarchy:
Unified cache 32 KB unified cache
SRAM 128 KB of internal SRAM
Flash 3 MB flash memory
The fastest accesses are to the unified cache.Both the internal SRAM and the flash memory hold
instructions and data. The external bus interface is designed to support most of the standard memories used
with the MPC5xx family.
The complex I/O timer functions of the MPC5500 family are performed by two enhanced time processor
unit engines (eTPUs). Each eTPU engine controls 32 hardware channels. The eTPU has been enhanced
over the TPU by providing 24-bit timers, double-action hardware channels, a variable number of
parameters per channel, angle clock hardware, and additional control and arithmetic instructions. Each
eTPU is programmed using a high-level programming language.
The timer functions of the MPC5500 family are performed by the enhanced modular input/output system
(eMIOS). The eMIOS’ 24 hardware channels are capable of single action, double action, pulse-width
modulation (PWM), and modulus counter operation. Motor control capabilities include edge-aligned and
center-aligned PWM.
Off-chip communication is performed by a suite of serial protocols including:
• 4 controller area networks (FlexCANs);
• 4 enhanced deserial/serial peripheral interface (DSPIs); and
• 2 enhanced serial communications interfaces (eSCIs).