NXP Semiconductors MPC5566, Reference Manual

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System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 6-17
The following table describes the fields in the DMA interrupt request enable register:
6.3.1.6 DMA/Interrupt Request Select Register (SIU_DIRSR)
The SIU_DIRSR selects between a DMA or interrupt request for events on the IRQ[0]–IRQ[3] inputs. If
the IRQ flag bits are set in the external IRQ status register (SIU_EISR) and the DMA/interrupt request
enable register (SIU_DIRER), then the select bit in the DMA interrupt request select register
(SIU_DIRSR) determines whether a DMA or interrupt request is asserted.
The following table describes the fields of the request select register:
Table 6-12. SIU_DIRER Field Descriptions
Field Description
0–15 Reserved
16–31
EIRE n
External interrupt request enable n. Enables the assertion of the interrupt request from the SIU to the interrupt
controller when an edge-triggered event occurs on the IRQ[ n ] pin.
0 External interrupt request is disabled.
1 External interrupt request is enabled.
Address: Base + 0x001C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0
DIRS
3
DIRS
2
DIRS
1
DIRS
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 6-7. DMA/Interrupt Request Select Register (SIU_DIRSR)
Table 6-13. SIU_DIRSR Field Descriptions
Field Description
0–27 Reserved
28–31
DIRS n
DMA interrupt request select n. Selects between a DMA transfer or external interrupt request when an
edge-triggered event occurs on the corresponding IRQ[ n ] pin.
0 Interrupt request is selected.
1 DMA request is selected.Reserved