NXP Semiconductors MPC5566, Reference Manual

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e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-16 Freescale Semiconductor
3.3.1.3 Effective to Real Address Translation
Instruction accesses are generated by sequential instruction fetches or due to a change in program flow
(branches and interrupts). Data accesses are generated by load, store, and cache management instructions.
The instruction fetch, branch, and load/store units generate 32-bit effective addresses. The MMU translates
this effective address to a 32-bit real address which is then used for memory accesses.
Figure 3-5 shows
the effective to real address translation flow.
Figure 3-5. Effective to Real Address Translation Flow
3.3.1.4 Permissions
The application software can restrict access to virtual pages by selectively granting permissions for user
mode read, write, and execute, and supervisor mode read, write, and execute on a per-page basis. For
example, program code might be execute-only and data structures can be mapped as
read/write/no-execute.
The following access control bits support selective permissions for access control:
• SR—Supervisor read permission. Allows loads and load-type cache management instructions to
access the page while in supervisor mode.
• SW—Supervisor write permission. Allows stores and store-type cache management instructions to
access the page while in supervisor mode.
• SX—Supervisor execute permission. Allows instruction fetches to access the page and instructions
to be executed from the page while in supervisor mode.
• UR—User read permission. Allows loads and load-type cache management instructions to access
the page while in user mode.
• UW—User write permission. Allows stores and store-type cache management instructions to
access the page while in user mode.
32-bit effective address
32-bit real address
Virtual Address
PID Effective page address Offset
0 31
TLB
multiple-entry
MSR[IS] for instruction fetch
AS
MSR[DS] for data access
RPN field of matching entry
n–1 n
Real page number Offset
0 31
NOTE: n = 32–log
2
(page size)
n
≥
20
n = 20 for 4-KB page size
n–1 n