NXP Semiconductors MPC5566, Reference Manual

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System Integration Unit (SIU)
MPC5566 Microcontroller Reference Manual, Rev. 2
6-88 Freescale Semiconductor
rate control and GPIO[206:207] are fast pad types with drive strength control. The PA bit is not
implemented for this PCR because GPIO is the only pin function.
Figure 6-115. GPIO[205] Pad Configuration Registers (SIU_PCR205)
6.3.1.115 Pad Configuration Registers 206–207 (SIU_PCR206–SIU_PCR207)
The SIU_PCR206–SIU_PCR207 registers control the function, direction, and electrical attributes of
GPIO[206:207]. These registers are separate from the PCR for GPIO[205] since GPIO[206:207] are fast
pad types with drive strength control and GPIO[205] is a medium pad type with slew rate control. The PA
bit is not implemented for these PCRs since GPIO is the only function.
NOTE
The GPIO[206:207] can trigger the ADCs. For ETRIG functionality, set
these pins to GPIO, and then select the GPIO ADC trigger in the
SIU_ETISR register. The input source for each SIN, SS, SCK, and trigger
signal is individually specified in the DSPI input select register
(SIU_DISR).
Refer to Section 6.3.1.161, “eQADC Trigger Input Select Register
(SIU_ETISR) .”
Figure 6-116. GPIO[206:207] Pad Configuration Registers (SIU_PCR206–SIU_PCR207)
Address: Base + 0x01DA Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0
OBE
1
1
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. When configured as
GPDI, set the IBE bit to 1.
0 0
ODE HYS SRC WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1
Address: Base + (0x01DC–0x01DE) Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0
OBE
1
1
When configured as GPDO, set the OBE bit to 1.
IBE
2
2
When the pad is configured as an output, set the IBE bit to 1 to show the pin state in the GPDI register. When configured as
GPDI, set the IBE bit to 1.
DSC ODE HYS
0 0
WPE WPS
W
RESET: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1