NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-28 Freescale Semiconductor
15.3.4.3 FIFO Receive Bound Register (FRBR)
The FRBR is a 32-bit register with one 8-bit field that the application can read to determine the upper
address bound of the FIFO RAM. Drivers can use this value, along with the FRSR register, to divide the
available FIFO RAM between the transmit and receive data paths.
15.3.4.3.1 FIFO Receive Start Register (FRSR)
The FRSR is a 32-bit register with one 8-bit field programmed by the application to indicate the starting
address of the receive FIFO. FRSR marks the boundary between the transmit and receive FIFOs. The
transmit FIFO uses addresses from the start of the FIFO to the location four bytes before the address
programmed into the FRSR. The receive FIFO uses addresses from FRSR to FRBR inclusive.
The FRSR register is initialized by hardware at reset. FRSR only needs to be written to change the default
value.
Table 15-22. TFWR Field Descriptions
Field Descriptions
0–29 Reserved, must be cleared.
30–31
X_WMRK
Number of bytes written to transmit FIFO before transmission of a frame begins
0x 64 bytes written
10 128 bytes written
11 192 bytes written
Address Base + 0x014C Access: RO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 R_BOUND 0 0
W
Reset 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0
Figure 15-23. FIFO Receive Bound Register (FRBR)
Table 15-23. FRBR Field Descriptions
Field Descriptions
0–21 Reserved, read as 0 (except bit 10, which is read as 1).
22–29
R_BOUND
Read-only. Highest valid FIFO RAM address.
30–31 Reserved, must be cleared.