NXP Semiconductors MPC5566, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-21
17.3.1.8 eMIOS Channel Status Register (EMIOS_CSR n )
EMIOS_CSR n reflects the status of the UC input/output signals and the overflow condition of the internal
counter, as well as the occurrence of a trigger event.
The following table describes the fields in the eMIOS channel status register:
Address: UC n Base + 0x0010 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R OVR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R OVFL 0 0 0 0 0 0 0 0 0 0 0 0 UCIN UCOUT FLAG
W w1c w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-9. eMIOS Channel Status Register (EMIOS_CSR n )
Table 17-11. EMIOS_CSR n Field Descriptions
Field Description
0
OVR
Overrun. Indicates a FLAG was generated when the FLAG bit was set to 1. To clear the OVR bit: write 1 to
clear the bit to 0, or clear the FLAG bit to 0, which also clears the OVR bit.
0 Overrun has not occurred
1 Overrun has occurred
1–15 Reserved.
16
OVFL
Overflow. Indicates that an overflow occurred in the internal counter. OVFL is cleared by writing a 1 to it.
0 No overflow
1 An overflow had occurred
17–28 Reserved.
29
UCIN
Unified channel input pin. Reflects the input pin state after being filtered and synchronized.
30
UCOUT
Unified channel output pin. The UCOUT bit reflects the output pin state.
31
FLAG
FLAG. Set when an input capture or a match event in the comparators occurs. Write a 1 to clear this bit to 0.
0 FLAG cleared
1 FLAG set event has occurred
Note: When EMIOS_CCR[DMA] bit is set, the FLAG bit is cleared by the eDMA controller.