NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-50 Freescale Semiconductor
Table 12-21 lists the patterns of the data transfer for write cycles when accesses are initiated by the MCU.
The bytes indicated as ‘—’ are not driven during that write cycle.
12.4.2.8 Arbitration
The external bus design provides for a single bus master at any one time, either the MCU or an external
device. One of the external devices on the bus has the capability of becoming bus master for the external
bus. Bus arbitration be handled either by an external central bus arbiter or by the internal on-chip arbiter.
The arbitration configuration (external or internal) is set via the EARB bit in the EBI_MCR.
Each bus master must have bus request, bus grant, and bus busy signals. The signals are described in detail
in Section 12.2.1, “Detailed Signal Descriptions .” The device that needs the bus asserts the bus request
(BR) signal. The device then waits for the arbiter to assert the bus grant (BG) signal. In addition, the new
master must sample the bus busy (BB) signal to ensure that no other master is driving the bus before it can
assert bus busy to assume ownership of the bus. The new master must sample bus busy negated for two
cycles before asserting bus busy, to avoid any potential conflicts. Any time the arbiter has taken the bus
grant away from the master, and the master wants to execute a new cycle, the master must re-arbitrate
before a new cycle can begin. The EBI, however, whether the internal or external arbiter is used,
guarantees data coherency for access to a small port size and for decomposed bursts. This means that the
EBI does not release the bus before the completion of the transactions which are considered as atomic.
Figure 12-32 describes the basic protocol for bus arbitration.
Table 12-21. Data Bus Contents for Write Cycles
Transfer
Size
TSIZ[0:1]
Address 32-Bit Port Size 16-Bit Port Size
1
1
Also applies when DBM = 1 for 16-bit data bus mode.
A[30] A[31] D[0:7] D[8:15] D[16:23] D[24:31] D[0:7] D[8:15]
Byte 01 0 0 OP0 — — — OP0 —
01 0 1 OP1 OP1 — — — OP1
01 1 0 OP2 — OP2 — OP2 —
01 1 1 OP3 OP3 — OP3 — OP3
16-bit 10 0 0 OP0 OP1 — — OP0 OP1
10 1 0 OP2 OP3 OP2 OP3 OP2 OP3
32-bit 00 0 0 OP0 OP1 OP2 OP3 OP0 or OP2
2
2
This case consists of two 16-bit external transactions, the first writing OP0 and OP1, the second writing OP2 and OP3.
OP1 or OP3