NXP Semiconductors MPC5566, Reference Manual

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Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5566 Microcontroller Reference Manual, Rev. 2
19-22 Freescale Semiconductor
19.3.2.8 eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISR n )
The EQADC_FISRs contain flag and status bits for each CFIFO and RFIFO pair. Writing 1 to a flag bit
clears it. Writing 0 has no effect. Status bits are read only. These bits indicate the status of the FIFO itself.
Address: Base + 0x0070 (EQADC_FISR0)
Base + 0x0074 (EQADC_FISR1)
Base + 0x0078 (EQADC_FISR2)
Base + 0x007C (EQADC_FISR3)
Base + 0x0080 (EQADC_FISR4)
Base + 0x0084 (EQADC_FISR5) Access: R/W1c
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R NCF n TORF n PF n EOQF n CFUF n SSS n CFFF n 0 0 0 0 0 RFOF n 0 RFDF n 0
W w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CFCTR n TNXTPTR n RFCTR n POPNXTPTR n
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 19-9. eQADC FIFO and Interrupt Status Registers 0–5 (EQADC_FISR n )
Table 19-12. EQADC_FISR n Field Descriptions
Field Description
0
NCF n
Non-coherency flag n . NCF n is set whenever a command sequence being transferred through CFIFO n becomes
non-coherent. If NCIE n in EQADC_IDCRn (Refer to Section 19.3.2.7, “eQADC Interrupt and eDMA Control
Registers 0–5 (EQADC_IDCRn) ”) and NCF n are asserted, an interrupt request is generated. Writing a 1 clears
NCF n . Writing a 0 has no effect. More for information on non-coherency refer to Section 19.4.3.6.5, “Command
Sequence Non-Coherency Detection .”
0 Command sequence being transferred by CFIFO n is coherent
1 Command sequence being transferred by CFIFO n became non-coherent
Note: Non-coherency means that a command in the command FIFO was not immediately executed, but delayed.
This may occur if the command is pre-empted, where a higher priority queue is triggered and has a competing
conversion command for the same converter.
1
TORF n
Trigger overrun flag for CFIFO n . TORF n is set when trigger overrun occurs for the specified CFIFO in edge or level
trigger mode. Trigger overrun occurs when an already triggered CFIFO receives an additional trigger. When
EQADC_IDCRn[TORIE
n] is set (Refer to Section 19.3.2.7, “eQADC Interrupt and eDMA Control Registers 0–5
(EQADC_IDCRn) ”) and TORF n are asserted, an interrupt request is generated.
Apart from generating an independent interrupt request for a CFIFO n trigger overrun event, the eQADC also
provides a combined interrupt at which the result FIFO overflow interrupt, the command FIFO underflow interrupt,
and the command FIFO trigger overrun Interrupt requests of all CFIFOs are ORed. When RFOIE
n , CFUIE n , and
TORIE n are all asserted, this combined interrupt request is asserted whenever one of the following 18 flags becomes
asserted: RFOF n , CFUF n , and TORF n (assuming that all interrupts are enabled). Refer to Section 19.4.7, “eQADC
eDMA/Interrupt Request ,” for details.
Write 1 to clear the TORF n bit. Writing 0 has no effect.
0 No trigger overrun occurred
1 Trigger overrun occurred
Note: The trigger overrun flag is not set for CFIFOs configured for software trigger mode.