NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-26 Freescale Semiconductor
The following table describes the fields in the DSPI pop receive FIFO register:
20.3.2.8 DSPI Transmit FIFO Registers 0–3 (DSPI x _TXFR n )
The DSPI x _TXFR n registers provide visibility into the TX FIFO for debugging purposes. Each register is
an entry in the TX FIFO. The registers are read-only and cannot be modified. Reading the DSPI x _TXFR n
registers does not alter the state of the TX FIFO. The MCU uses four registers to implement the TX FIFO,
that is DSPI
x _TXFR0–DSPI x _TXFR3 are used.
The following table describes the fields in the DSPI transmit FIFO register:
Table 20-9. DSPI x _POPR Field Descriptions
Field Description
0–15 Reserved, must be cleared.
16–31
RXDATA
[0:15]
Received data. The RXDATA field contains the SPI data from the RX FIFO entry pointed to by the pop next data
pointer (POPNXTPTR).
Address:
Base + 0x003C (DSPI
x _TXFR0)
Base + 0x0040 (DSPI x _TXFR1)
Base + 0x0044 (DSPI x _TXFR2)
Base + 0x0048 (DSPI x _TXFR3)
Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R TXCMD
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R TXDATA
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-10. DSPI Transmit FIFO Register 0–3 (DSPI x _TXFR n )
Table 20-10. DSPI x _TXFR n Field Descriptions
Field Description
0–15
TXCMD
[0:15]
Transmit command. Contains the command that sets the transfer attributes for the SPI data. See Section 20.3.2.6,
“DSPI PUSH TX FIFO Register (DSPIx_PUSHR) ,” for details on the command field.
16–31
TXDATA
[0:15]
Transmit data. Contains the SPI data to be shifted out.