NXP Semiconductors MPC5566, Reference Manual

Page: 612 / 1268

Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-3
15.1.2 Overview
The Ethernet media access controller (MAC) is designed to support both 10 and 100 Mbps
Ethernet/IEEE
®
802.3 networks. An external transceiver interface and transceiver function are required
to complete the interface to the media. The FEC supports three different standard MAC-PHY (physical)
interfaces for connection to an external Ethernet transceiver. The FEC supports the 10/100 Mbps MII and
the 10 Mbps-only 7-wire interface, which uses a subset of the MII signals.
The descriptor controller is RISC-based and provides the following FEC functions:
• Initialization (the internal registers not initialized by the application or hardware)
• High-level control of the DMA channels (initiating DMA transfers)
• Interpreting buffer descriptors
• Address recognition for receive frames
• Random number generation for transmit collision backoff timer
NOTE
DMA references in this section refer to the FEC DMA engine used to
transfer FEC data only. It is not related to the DMA controller described in
Chapter 9, “Enhanced Direct Memory Access (eDMA) .”
The RAM is the focal point of all data flow in the fast Ethernet controller and is divided into transmit and
receive FIFOs. The FIFO boundaries are programmable using the FRSR register. Application data flows
to/from the DMA block from/to the receive/transmit FIFOs. Transmit data flows from the transmit FIFO
into the transmit block and receive data flows from the receive block into the receive FIFO.
You control the FEC by writing, through the slave interface module, to control registers located in each
block. The CSR (control and status register) block provides global control (such as Ethernet reset and
enable) and interrupt handling registers.
The MII block provides a serial channel for control/status communication with the external physical layer
device (transceiver). This serial channel consists of the MDC (management data clock) and MDIO
(management data input/output) lines of the MII interface.
The DMA block provides multiple channels allowing transmit data, transmit descriptor, receive data, and
receive descriptor accesses to run independently.
The transmit and receive blocks provide the Ethernet MAC functionality (with some assist from
microcode).
The message information block (MIB) maintains counters for a variety of network events and statistics. It
is not necessary for operation of the FEC but provides valuable counters for network management. The
counters supported are the RMON (RFC 1757) Ethernet Statistics group and some of the IEEE
®
802.3
counters.