
Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
21-30
Freescale Semiconductor
21.4.5.5.2
Fast Data Tolerance
shows how much a fast received frame can be misaligned. The fast stop bit ends at RT10
instead of RT16 but is still sampled at RT8, RT9, and RT10.
Figure 21-20. Fast Data
For an 8-bit data character, data sampling of the stop bit takes the receiver 154 RT cycles, as is shown
below:
With the misaligned character shown in
, the receiver counts 154 RT cycles at the point when
the count of the transmitting device is 10 bit times x 16 RT cycles = 160 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 8-bit
character with no errors is 3.40%, as is shown below:
For a 9-bit data character, data sampling of the stop bit takes the receiver 170 RT cycles, as shown below:
With the misaligned character shown in
, the receiver counts 170 RT cycles at the point when
the count of the transmitting device is 11 bit times x 16 RT cycles = 176 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a fast 9-bit
character with no errors is 3.40%, as is shown below:
21.4.5.6
Receiver Wake-up
The receiver can be put into a standby state, which disregards all input requests targeted for other receivers
in multiple-receiver systems. Setting the receiver wake-up bit (RWU) in eSCI control register 1
(ESCI
x
_CR1) puts the receiver into the standby state, which disregards all receiver interrupts tar. The eSCI
loads the received data into the ESCI
x
_DR, but does not set the receive data register full (RDRF) flag.
RT1
Receiver
RT clock
RT2 RT3 RT4 RT5 RT6 RT7 RT8 RT9 RT10 RT11 RT12 RT13 RT14 RT15 RT16
STOP
IDLE or next frame
Data samples
9 bit times
16 RT cycles
10 RT cycles
+
×
154 RT cycles
=
160 – 154
160
--------------------------
100
×
3.40%
=
10 bit times
16 RT cycles
10 RT cycles
+
×
170 RT cycles
=
176 – 170
176
--------------------------
100
×
3.40%
=
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...