Addendum for Revision 2.0
MPC5566 Reference Manual Addendum, Rev. 2
Freescale Semiconductor
7
Section 10.4.2.1.4, “Priority
Comparator Submodule”/
Page 10-30
Add the following paragraph to this section:
One consequence of the priority comparator design is that once a higher priority interrupt is
captured, it must be acknowledged by the CPU before a subsequent interrupt request of even
higher priority can be captured. For example, if the CPU is executing a priority level 1 interrupt,
and a priority level 2 interrupt request is captured by the INTC, followed shortly by a priority level
3 interrupt request to the INTC, the level 2 interrupt must be acknowledged by the CPU before a
new level 3 interrupt will be generated.
Section 10.5.5.2, “Ensuring
Coherency”/ Page 10-37
Move the content of this section under a new heading Section 10.5.5.2.1, “Interrupt with Blocked
Priority”.
Add the following paragraph to this section:
Section 10.5.5.2.2: Raised Priority Preserved
Before the instruction after the GetResource system service executes, all pending transactions
have completed. These pending transactions can include an ISR for a peripheral or software
settable interrupt request whose priority was equal to or lower than the raised priority. Also,
during the epilog of the interrupt exception handler for this preempting ISR, the raised priority
has been restored from the LIFO to PRI in INTC_CPR. The shared coherent data block now can
be accessed coherently. Following figure shows the timing diagram for this scenario, and the
table explains the events. The example is for software vector mode, but except for the method of
retrieving the vector and acknowledging the interrupt request to the processor, hardware vector
mode is identical.
Raised Priority Preserved Timing Diagram
Table 1. MPC5566RM Rev 2.0 addendum
Location
Description
Last In / First Out
Entry in LIFO
Write
INTC_CPR
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
PRI in
INTC_CPR
Peripheral Interrupt
Request 100
0
108
1
208
2
3
Peripheral Interrupt
Request 200
0
3
0
3
A
B
C
D
E
F
G
H
I
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
