NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
15-30 Freescale Semiconductor
15.3.4.3.3 Transmit Buffer Descriptor Ring Start (ETDSR)
The ETDSR is written by the application. It provides a pointer to the start of the circular transmit buffer
descriptor queue in external memory. This pointer must be 32-bit aligned; however, it is recommended it
be made 128-bit aligned (evenly divisible by 16). Bits 30 and 31 must be written to 0 by the application.
Non-zero values in these two bit positions are ignored by the hardware.
This register is not reset and must be initialized by the application prior to operation.
15.3.4.3.4 Receive Buffer Size Register (EMRBR)
The EMRBR is a 32-bit register with one 7-bit field programmed by the application. The EMRBR register
dictates the maximum size of all receive buffers. Note that because receive frames are truncated at 2K–1
byte, only bits 21–27 are used. This value must take into consideration that the receive CRC is always
written into the last receive buffer. To allow one maximum size frame per buffer, EMRBR must be set to
RCR[MAX_FL] or larger. The EMRBR must be evenly divisible by 16. To insure this, bits 28-31 are
Table 15-25. ERDSR Field Descriptions
Field Descriptions
0–29
R_DES_START
Pointer to start of receive buffer descriptor queue.
30–31 Reserved, must be cleared.
Address Base + 0x0184 Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
X_DES_START
W
Reset U
1
U U U U U U U U U U U U U U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
X_DES_START
0 0
W
Reset U U U U U U U U U U U U U U U U
1
“U” signifies a bit that is uninitialized.
Figure 15-26. Transmit Buffer Descriptor Ring Start Register (ETDSR)
Table 15-26. ETDSR Field Descriptions
Field Descriptions
0–29
X_DES_START
Pointer to start of transmit buffer descriptor queue.
30–31 Reserved, must be cleared.