NXP Semiconductors MPC5566, Reference Manual

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Enhanced Modular Input/Output Subsystem (eMIOS)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 17-13
17.3.1.6 eMIOS Channel Counter Register (EMIOS_CCNTR n )
The EMIOS_CCNTR n contains the value of the internal counter. When GPIO mode is selected or the
channel is frozen, the EMIOS_CCNTR n is readable and writable. For all others modes, the
EMIOS_CCNTR n is a read-only register. When entering some operating modes, this register is
automatically cleared.
Refer to Section 17.4.4.4, “Unified Channel Operating Modes ,” for details.
17.3.1.7 eMIOS Channel Control Register (EMIOS_CCR n )
The eMIOS_CCR n enables the setting of several control parameters for a unified channel. Among these
controls are the setting of a channel prescaler, channel mode selection, input trigger sensitivity and
filtering, interrupt and DMA request enabling, and output mode control.
Address: UC n Base + 0x0008 Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 C
W
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R C
W
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
In GPIO mode or freeze action, this register is writable.
Figure 17-7. eMIOS Channel Counter Register (EMIOS_CCNTR n )
Address: UC n Base + 0x000C Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
FREN ODIS ODISSL UCPRE
UCP
REN
DMA
0
IF FCK FEN
0
W
1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0
BSL EDSEL EDPOL MODE
W
1
FORCMA FORCMB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 17-8. eMIOS Channel Control Register (EMIOS_CCR n )