NXP Semiconductors MPC5566, Reference Manual

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Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 10-33
Figure 10-15. Hardware Vector Mode Handshaking Timing Diagram
10.5 Initialization and Application Information
10.5.1 Initialization Flow
After exiting reset, all of the PRI n fields in INTC priority select registers (INTC_PSR0–INTC_PSR329)
is zero, and PRI in INTC current priority register (INTC_CPR) is 15. These reset values prevent the INTC
from asserting the interrupt request to the processor. The enable or mask bits in the peripherals are reset
such that the peripheral interrupt requests are negated.
An initialization sequence that allows the peripheral and software settable interrupt requests to generate an
interrupt request to the processor is:
interrupt_request_initialization:
configure VTES and HVEN in INTC_MCR
configure VTBA in INTC_IACKR
raise the PRI n fields in INTC_PSR
n
set the enable bits or clear the mask bits for the peripheral interrupt requests
lower PRI in INTC_CPR to zero
enable processor recognition of interrupts
10.5.2 Interrupt Exception Handler
These example interrupt exception handlers use Power Architecture assembly code.
Clock
Interrupt Request
to Processor
Hardware Vector
Enable
Interrupt
Acknowledge
Interrupt Vector
Read
INTC_IACKR
Write
INTC_EOIR
INTVEC in
INTC_IACKR
PRI in
INTC_CPR
Peripheral Interrupt
Request 100
0
0 108
0
108
0 1