NXP Semiconductors MPC5566, Reference Manual

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Peripheral Bridge (PBRIDGE A and PBRIDGE B)
MPC5566 Microcontroller Reference Manual, Rev. 2
5-12 Freescale Semiconductor
5.4 Functional Description
The PBRIDGE serves as an interface between a system bus and the peripheral (slave) bus. It functions as
a protocol translator. Support is provided for generating a pair of 32-bit peripheral accesses when targeted
by a 64-bit system bus access. No other bus-sizing access support is provided.
Accesses that fall within the address space of the PBRIDGE are decoded to provide individual module
selects for peripheral devices on the slave bus interface.
5.4.1 Access Support
Aligned 64-bit accesses, aligned word and halfword accesses, as well as byte accesses are supported for
32-bit peripherals. Peripheral registers must not be misaligned, although no explicit checking is performed
by the PBRIDGE.
NOTE
Data accesses that cross a 32-bit boundary are not supported.
5.4.2 Peripheral Write Buffering
The PBRIDGE provides programmable write buffering capability to buffer write accesses in the
PBRIDGE for later completion, while terminating the system bus access early. This provides improved
performance in systems where frequent writes to a slow peripheral occur.
Write buffering is controllable on a per-master and per-peripheral basis. Enable write buffering for masters
and peripherals only when an error termination from the slave bus does not occur or is safe to ignore. When
write buffering is enabled, all accesses through the PBRIDGE must occur in sequence; bypassing buffered
writes is
not supported.
NOTE
Write buffering causes the processor core to believe that the write has
completed before it actually has completed in the peripheral. If write
buffering is enabled for a peripheral, the actual write takes an additional two
system clock cycles plus any additional system clock cycles that the register
needs. Most registers in the MPC5500 family delay the write by two clock
cycles, but some registers take longer. This early termination, as seen by the
processor core, can defeat the
mbar or msync instruction between the write
to clear a flag bit and the write to the INTC_EOIR. Therefore, if write
buffering is enabled for a peripheral that has a flag bit, insert instructions
between the
mbar or msync instruction and the write to the INTC_EOIR
that consumes at least the number of system clock cycles that the actual
write is delayed.
Refer to Section 10.4.3.1.2, “End-of-Interrupt Exception Handler .”