NXP Semiconductors MPC5566, Reference Manual

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MPC5566 Register Map
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor A-29
Reserved — — Base + (0x044C–0x044F)
eTPU A channel 5 configuration register ETPU_C5CR_A 32-bit Base + 0x0450
eTPU A channel 5 status and control register ETPU_C5SCR_A 32-bit Base + 0x0454
eTPU A channel 5 host service request register ETPU_C5HSRR_A 32-bit Base + 0x0458
Reserved — — Base + (0x045C–0x045F)
eTPU A channel 6 configuration register ETPU_C6CR_A 32-bit Base + 0x0460
eTPU A channel 6 status and control register ETPU_C6SCR_A 32-bit Base + 0x0464
eTPU A channel 6 host service request register ETPU_C6HSRR_A 32-bit Base + 0x0468
Reserved — — Base + (0x046C–0x046F)
eTPU A channel 7 configuration register ETPU_C7CR_A 32-bit Base + 0x0470
eTPU A channel 7 status and control register ETPU_C7SCR_A 32-bit Base + 0x0474
eTPU A channel 7 host service request register ETPU_C7HSRR_A 32-bit Base + 0x0478
Reserved — — Base + (0x047C–0x047F)
eTPU A channel 8 configuration register ETPU_C8CR_A 32-bit Base + 0x0480
eTPU A channel 8 status and control register ETPU_C8SCR_A 32-bit Base + 0x0484
eTPU A channel 8 host service request register ETPU_C8HSRR_A 32-bit Base + 0x0488
Reserved — — Base + (0x048C–0x048F)
eTPU A channel 9 configuration register ETPU_C9CR_A 32-bit Base + 0x0490
eTPU A channel 9 status and control register ETPU_C9SCR_A 32-bit Base + 0x0494
eTPU A channel 9 host service request register ETPU_C9HSRR_A 32-bit Base + 0x0498
Reserved — — Base + (0x049C–0x049F)
eTPU A channel 10 configuration register ETPU_C10CR_A 32-bit Base + 0x04A0
eTPU A channel 10 status and control register ETPU_C10SCR_A 32-bit Base + 0x04A4
eTPU A channel 10 host service request register ETPU_C10HSRR_A 32-bit Base + 0x04A8
Reserved — — Base + (0x04AC–0x04AF)
eTPU A channel 11 configuration register ETPU_C11CR_A 32-bit Base + 0x04B0
eTPU A channel 11 status and control register ETPU_C11SCR_A 32-bit Base + 0x04B4
eTPU A channel 11 host service request register ETPU_C11HSRR_A 32-bit Base + 0x04B8
Reserved — — Base + (0x04BC–0x04BF)
eTPU A channel 12 configuration register ETPU_C12CR_A 32-bit Base + 0x04C0
eTPU A channel 12 status and control register ETPU_C12SCR_A 32-bit Base + 0x04C4
eTPU A channel 12 host service request register ETPU_C12HSRR_A 32-bit Base + 0x04C8
Table A-2. MPC5566 Detailed Register Map (continued)
Register Description Register Name
Used
Size
Address