NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-31
forced low. To minimize bus utilization (descriptor fetches) it is recommended that EMRBR be greater
than or equal to 256 bytes.
The EMRBR register does not reset, and must be initialized by the application.
15.4 Functional Description
This section describes the operation of the FEC, beginning with the hardware and software initialization
sequence, then the software (Ethernet driver) interface for transmitting and receiving frames.
Following the software initialization and operation sections are sections providing a detailed description
of the functions of the FEC.
15.4.1 Initialization Sequence
This section describes which registers are reset due to hardware reset, which are reset by the FEC RISC,
and what locations the application must initialize prior to enabling the FEC.
15.4.1.1 Hardware Controlled Initialization
In the FEC, registers and control logic that generate interrupts are reset by hardware. A hardware reset
deasserts output signals and resets general configuration bits.
Address: Base + 0x0188 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset U
1
U U U U U U U U U U U U U U U
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0
R_BUF_SIZE
0 0 0 0
W
Reset U U U U U U U U U U U U U U U U
1
“U” signifies a bit that is uninitialized.
Figure 15-27. Receive Buffer Size Register (EMRBR)
Table 15-27. EMRBR Field Descriptions
Field Descriptions
0–20 Reserved, must be written to 0 by the host processor.
21–27
R_BUF_SIZE
Receive buffer size.
28–31 Reserved, must be written to 0 by the host processor.