NXP Semiconductors MPC5566, Reference Manual

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Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-15
priority level can be raised temporarily so that no task can preempt another task that shares the same
resource.
Multiple processors can assert interrupt requests to each other through software settable interrupt requests
(by using application software to assert requests). These maskable interrupt requests can divide the
software into a high-priority portion and a low-priority portion for servicing the interrupt requests. The
high-priority portion is initiated by a peripheral interrupt request, but then the ISR asserts a software
settable interrupt request to finish the servicing in a lower priority ISR.
1.5.5 Frequency Modulated Phase-Locking Loop (FMPLL)
The frequency modulated phase-locking loop (FMPLL) generates high-speed system clocks from an
8–20 MHz crystal oscillator or an external clock generator. Furthermore, the FMPLL supports
programmable frequency modulation of the system clock. The PLL multiplication factor, output clock
divider ratio, modulation depth, and modulation rate are all software configurable.
1.5.6 External Bus Interface (EBI)
The external bus interface (EBI) controls data transfer across the crossbar switch to/from memories or
peripherals in the external address space. The EBI is available on the 416 BGA package only. The EBI also
enables an external master to access internal address space. The EBI includes a memory controller that
generates interface signals to support a variety of external memories. The memory controller supports
single data rate (SDR) burst mode flash, external SRAM, and asynchronous memories. In addition, the
EBI supports up to four regions (via chip selects), along with programmed region-specific attributes.
1.5.7 System Integration Unit (SIU)
The device’s system integration unit (SIU) controls MCU reset configuration, pad configuration, external
interrupt, general-purpose I/O (GPIO), internal peripheral multiplexing, and the system reset operation.
The reset configuration module contains the external pin boot configuration logic. The pad configuration
module controls the static electrical characteristics of I/O pins. The GPIO module provides uniform and
discrete input/output control of the I/O pins of the MCU. The reset controller performs reset monitoring
of internal and external reset sources, and drives the RSTOUT pin. The SIU is accessed by the e200z6 core
through the crossbar switch.
1.5.8 Error Correction Status Module (ECSM)
The error correction status module (ECSM) provides status information regarding platform memory errors
reported by error-correcting codes.
1.5.9 Flash Memory
The MPC5566 provides 3 MB of programmable, non-volatile, flash memory storage. Non-volatile
memory (NVM) can be used for instruction and/or data storage.