NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-9
15.3.4 Registers
15.3.4.1 FEC Burst Optimization Master Control Register (FBOMCR)
Although not an FEC register, the FEC burst optimization master control register (FBOMCR) controls
FEC burst optimization behavior on the system bus, hence it is described in this section.
FEC registers are described in Section 15.3.4.2.1, “Ethernet Interrupt Event Register (EIR) ” through
Section 15.3.4.3.4, “Receive Buffer Size Register (EMRBR) .”
To increase throughput, the FEC interface to the system bus can accumulate read requests or writes to burst
those transfers on the system bus. The FBOMCR determines the XBAR ports for which this bursting is
enabled, as well as whether the bursting is for reads, writes, or both. FBOMCR also controls how errors
for writes are handled. The FBOMCR address is 0xFFF4_0024, which is the ECSM base address
0xFFF4_0000 plus the offset of 0x0024.
Table 15-3 describes the fields and functions of the FEC burst optimization register:
Address: Base + 0x0024 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R FXS
BE0
FXS
BE1 0 FXS
BE3 0 0 FXS
BE6 FXS
BE7 RBEN WBEN ACC
ERR 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-2. FEC Burst Optimization Master Control Register (FBOMCR)
Table 15-3. FBOMCR Field Descriptions
Bits Name Description
0–7 FXSBE n
[0:7]
FXSBE – FEC XBAR slave burst enable. FXSBE n enables bursting by the
FEC interface to the XBAR slave port controlled by that respective FXSBE n
bit. If FXSBE n is asserted, then that XBAR slave port enabled by the bit can
accept the bursts allowed by RBEN and WBEN. Otherwise, the FEC
interface does not burst to the XBAR slave port controlled by that respective
FXSBE
n bit. Read bursts from that XBAR slave port are enabled by RBEN.
Write bursts to that XBAR slave port are enabled by WBEN.
FXSBE n assignments to XBAR slave ports:
FXSBE0 = Flash
FXSBE1 = EBI
FXSBE3 = Internal SRAM
FXSBE6 = Peripheral bridge A
FXSBE7 = Peripheral bridge B
8 RBEN Global read burst enable from XBAR slave port designated by FXSBE n
0 = Read bursting from all XBAR slave ports is disabled.
1 = Read bursting is enabled from any XBAR slave port whose FXSBE
n bit
is asserted.