NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-35
If a collision occurs during transmission of the frame (half duplex mode), the Ethernet controller follows
the specified backoff procedures and attempts to retransmit the frame until the retry limit is reached. The
transmit FIFO stores at least the first 64 bytes of the transmit frame, so that they do not have to be retrieved
from system memory in case of a collision. This improves bus utilization and latency in case immediate
retransmission is necessary.
When all the frame data has been transmitted, the FCS (frame check sequence or 32-bit cyclic redundancy
check, CRC) bytes are appended if the TC bit is set in the transmit frame control word. If the ABC bit is
set in the transmit frame control word, an invalid CRC is appended to the frame data regardless of the TC
bit value. Following the transmission of the CRC, the Ethernet controller writes the frame status
information to the MIB block. Short frames are automatically padded by the transmit logic (if the TC bit
in the transmit buffer descriptor for the end of frame buffer = 1).
Both buffer (TXB) and frame (TFINT) interrupts can be generated as determined by the settings in the
EIMR.
The transmit error interrupts are HBERR, BABT, LATE_COL, COL_RETRY_LIM, and XFIFO_UN. If
the transmit frame length exceeds MAX_FL bytes, the BABT interrupt is asserted but the entire frame is
transmitted (no truncation).
To pause transmission, set the GTS (graceful transmit stop) bit in the TCR register. When the TCR[GTS]
is set, the FEC transmitter stops immediately if transmission is not in progress; otherwise, it continues
transmission until the current frame either finishes or terminates with a collision. After the transmitter has
stopped, the GRA (graceful stop complete) interrupt is asserted. If TCR[GTS] is cleared, the FEC resumes
transmission with the next frame.
The Ethernet controller transmits bytes least significant bit first.
15.4.7 FEC Frame Reception
The FEC receiver is designed to work with almost no intervention from the host and can perform address
recognition, CRC checking, short frame checking, and maximum frame length checking.
When the driver enables the FEC receiver by asserting ECR[ETHER_EN], the FEC starts processing
receive frames immediately. When FEC_RX_DV asserts, the receiver first checks for a valid PA/SFD
header. If the PA/SFD is valid, it is stripped and the frame is processed by the receiver. If no valid PA/SFD
is found, the frame is ignored.
In serial mode, the first 16 bit times of FEC_RXD0 following assertion of FEC_RX_DV are ignored.
Following the first 16 bit times the data sequence is checked for alternating 1 and 0. If a 11 or 00 data
sequence is detected during bit times 17 to 21, the remainder of the frame is ignored. After bit time 21, the
data sequence is monitored for a valid SFD (11). If a 00 is detected, the frame is rejected. When a 11 is
detected, the PA/SFD sequence is complete.
In MII mode, the receiver checks for at least one byte matching the SFD. Zero or more PA bytes can occur,
but if a 00 bit sequence is detected prior to the SFD byte, the frame is ignored.
After the first 6 bytes of the frame have been received, the FEC performs address recognition on the frame.