NXP Semiconductors MPC5566, Reference Manual

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Nexus
MPC5566 Microcontroller Reference Manual, Rev. 2
25-36 Freescale Semiconductor
25.11.1 Port Configuration Register (PCR)
The Port Configuration Register (PCR) controls the basic port functions for all Nexus modules in a
multi-Nexus environment. This includes clock control and auxiliary port width. All bits in this register are
writable only once after system reset.
Figure 25-14. Port Configuration Register
NOTE
The CSC and PCR registers are in separate system module for a
multi-Nexus environment. If the e200z6 Nexus3 module is the only Nexus
module, the CSC and PCR registers are not implemented, and the e200z6
Nexus3 development control register 1 (DC1) set the Nexus port
functionality.
OPC
0
MCK_EN
MCK_DIV
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Nexus Reg# - PCR_INDEX; R/W; Reset - 0x0
Table 25-25. Port Configuration Register Fields
PCR[31] OPC OPC — Output Port Mode Control
0 = Reduced Port Mode configuration (minimum # nex_mdo[n:0]
pins)
1 = Full Port Mode configuration (max# nex_mdo[n:0] pins defined
by SOC)
PCR[30] — Reserved for future functionality
PCR[29] MCK_EN MCK_EN — MCKO Clock enable
0 = nex_mcko is disabled
1 = nex_mcko is enabled
PCR[28:26] MCK_DIV MCK_DIV — MCKO Clock Divide Ratio (read note that follows this table)
000 = nex_mcko is 1x processor clock frequency.
001 = nex_mcko is 1/2x processor clock frequency.
010 = Reserved (defaults to 1/2x processor clock frequency.)
011 =
nex_mcko is 1/4x processor clock frequency.
100–110 = Reserved (defaults to 1/2x processor clock frequency.)
111 =
nex_mcko is 1/8x processor clock frequency.
PCR[25:0] — Reserved for future functionality