NXP Semiconductors MPC5566, Reference Manual

Page: 1019 / 1268

Enhanced Serial Communication Interface (eSCI)
MPC5566 Microcontroller Reference Manual, Rev. 2
21-22 Freescale Semiconductor
To initiate an eSCI transmission:
1. Configure the eSCI:
a) Turn on the module by clearing ESCI x _CR2[MDIS] if this bit is set.
b) Select a baud rate. Write this value to the eSCI control register 1 (ESCI x _CR1) to start the baud
rate generator. Remember that the baud rate generator is disabled when the ESCI x _CR1[SBR]
field is zero. When using 8-bit writes, writes to the ESCI x _CR1[0–7] have no effect without
also writing to ESCI x _CR1[8–15].
c) Write to ESCIx_CR1 to configure word length, parity, and other configuration bits
(LOOPS, RSRC, M, WAKE, ILT, PE, PT).
d) Enable the transmitter, interrupts, receive, and wake-up as required, by writing to the
ESCI x _CR1 register bits (TIE, TCIE, RIE, ILIE, TE, RE, RWU, SBK). A preamble or idle
character is shifted out of the transmitter shift register.
NOTE
A single 32-bit write to ESCI_CR1 can be used to perform steps b–d above.
2. Transmit procedure for each byte:
a) Poll the TDRE flag by reading the ESCI x _SR or responding to the TDRE interrupt. Keep in
mind that the TDRE bit resets to 1.
b) If the TDRE flag is set, software should then clear it, followed by writing the data to be
transmitted to ESCIx_DR, where the ninth bit is
written to the T8 bit in ESCIx_DR if the eSCI is in 9-bit data format.
3. Repeat step 2 for each subsequent transmission.
NOTE
The TDRE flag is set when the shift register is loaded with the next data to
transmit from ESCI
x _DR, which occurs approximately half-way through
the stop bit of the previous frame. This transfer occurs 9/16ths of a bit time
AFTER the start of the stop bit of the previous frame.
Toggling the TE bit from 0 to 1 automatically loads the transmit shift register with a preamble of 10 logic
1s (if M = 0) or 11 logic 1s (if M = 1). After the preamble shifts out, control logic transfers the data from
the eSCI data register into the transmit shift register. A logic 0 start bit automatically goes into the least
significant bit position of the transmit shift register. A logic 1 stop bit goes into the most significant bit
position.
The eSCI hardware supports odd or even parity. When parity is enabled, the most significant bit (Msb) of
the data character is the parity bit.
The transmit data register empty flag, TDRE, in the eSCI status register (ESCI x _SR) is set when the eSCI
data register transfers a byte to the transmit shift register. The TDRE flag indicates that the eSCI data
register can accept new data from the internal data bus. If the transmit interrupt enable bit (TIE), in eSCI
control register 1 (ESCI
x _CR1) is also set, the TDRE flag generates a transmit interrupt request.