Error Correction Status Module (ECSM)
MPC5566 Microcontroller Reference Manual, Rev. 2
8-6
Freescale Semiconductor
data write cycles, subsequent reads of the corrupt address locations generate ECC events, such as
double-bit noncorrectable errors that are terminated with an error response.
If an attempt to force a non-correctable error (by asserting ECSM_EEGR[FRCNCI] or
ECSM_EEGR[FRC1NCI]) and the ECSM_EEGR[ERRBIT] equals 64, then no data error is generated.
NOTE
Only values {0,0}, {1,0} and {0,1} are allowed for the two control bit
enables {FRCNCI, FR1NCI}. The value {1,1} causes undefined results.
Base + 0x004A
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
FRC
NCI
FR1
NCI
0
ERRBIT[0:6]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 8-3. ECC Error Generation (ECSM_EEGR) Register
Table 8-4. ECSM_EEGR Field Definitions
Field
Description
0–5
Reserved.
6
FRCNCI
Force internal SRAM continuous noncorrectable data errors.
0 No internal SRAM continuous 2-bit data errors are generated.
1 2-bit data errors in the internal SRAM are continuously generated.
The assertion of this bit forces the internal SRAM controller to create 2-bit data errors, as defined by the bit position
specified in ERRBIT[0:6] and the overall odd parity bit, continuously on every write operation.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
7
FR1NCI
Force internal SRAM one noncorrectable data errors.
0 No internal SRAM single 2-bit data errors are generated.
1 One 2-bit data error in internal SRAM is generated.
The assertion of this bit forces the internal SRAM controller to create one 2-bit data error, as defined by the bit
position specified in ERRBIT[0:6] and the overall odd parity bit, on the first write operation after this bit is set.
The normal ECC generation takes place in the internal SRAM controller, but then the polarity of the bit position
defined by ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly
re-enable the error generation logic.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
