NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
12-62 Freescale Semiconductor
Figure 12-39 and Figure 12-40 illustrate the basic flow of read and write external master accesses.
Figure 12-39. Basic Flow Diagram of an External Master Read Access
External Master EBI (Slave)
No
Yes
External
arbitration*
?
Request bus (BR)
Receives bus grant (BG)
Asserted from external arbiter**
Receives BB negated for 2 cycles
Negates BR if no other requests
No
Yes
External
master has
priority***
Negates BG if asserted
Asserts bus busy (BB)
if no other master is driving
Assert transfer start (TS)
drives address and attributes
?
Receives address
No
Yes
Address
in internal memory
map
?
Other shared device
drives data and asserts
transfer acknowledge (TA)
Receives data
Drives data
asserts
transfer acknowledge (TA)
This refers to whether the external master device is configured for external or internal arbitration.
*
External arbiter is the EBI unless a central arbiter device is used.
**
Determined by the internal arbiter of the external master device.
***