NXP Semiconductors MPC5566, Reference Manual

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External Bus Interface (EBI)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 12-5
NOTE
The internal bus grant input of the EBI is tied to a negated state. In a dual
controller system in which the EBI is programmed to External Master Mode
with external arbitration, if the CPU tries to access a memory region within
the EBI space, no bus grant is received, and the operation times out.
External master mode operation is described in Section 12.4.2.10, “Bus Operation in External Master
Mode .”
12.1.4.3 Module Disable Mode
The module disable mode is used for MCU power management. The clock to the non-memory mapped
logic in the EBI is stopped while in module disable mode. Requests (other than to memory-mapped logic)
must not be made to the EBI while it is in module disable mode, even if the clocks have not yet been shut
off. In this case, the behavior is undefined. Module disable mode is entered when MDIS = 1 in the
EBI_MCR.
12.1.4.4 Configurable Bus Speed Modes
In configurable bus speed modes, the external CLKOUT frequency is reduced to ½ or ¼ compared to the
internal system clock frequency. The EBI continues to operate according to the EBI mode selected, except
that the EBI drives and samples signals at the scaled CLKOUT frequency rate rather than the internal
system clock. This mode is selected by writing the external clock control register in the system integration
module (SIU_ECCR). The configurable bus speed modes supports both ½ or ¼ speed modes, meaning that
the external CLKOUT frequency is scaled (divided) by two or four compared with that of the internal
system clock, which remains unchanged.
NOTE
In a multi-master system with the PLL in dual-controller mode, only ½
speed mode is supported.
12.1.4.5 16-Bit Data Bus Mode
The EBI has an internal 32-bit data bus, but for MCUs that have only 16 data bus signals pinned out, or
for systems that use multiplexed signals (e.g. GPIO) on 16 of the 32 data pins, the EBI supports a 16-bit
data bus mode. In this mode, DATA[0:15] are the only data signals used by the EBI. To enter 16-bit data
bus mode, set the data bus mode field [DBM] in the EBI master control register (EBI_MCR[DBM]) to
one. The reset value of DBM is 0.
For EBI-mastered accesses, the operation in 16-bit data bus mode (EBI_MCR[DBM] = 1,
EBI_BR
n [PS] = x) is similar to a chip select access to a 16-bit port in 32-bit data bus mode
(EBI_MCR[DBM] = 0, EBI_BR n [PS] = 1), except for the case of an EBI-mastered non-chip select access
of exactly 32-bit size.
External master accesses and EBI-mastered non-chip select accesses of exactly 32-bit size are supported
using a two beat (16-bit) burst for both reads and writes. Except for chip-select (CS[
n ]) data transmissions,
all data transmissions that are not 32 bits are supported in standard non-burst fashion.