NXP Semiconductors MPC5566, Reference Manual

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Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 10-5
— 16 are reserved sources
• 9-bit unique vector for each interrupt request source in hardware vector mode.
• Each interrupt source can be programmed to one of 16 priorities.
• Preemption.
— Preemptive prioritized interrupt requests to processor.
— ISR at a higher priority preempts ISRs or tasks at lower priorities.
— Automatic pushing or popping of preempted priority to or from a LIFO.
— Ability to modify the ISR or task priority. Modifying the priority can be used to implement the
priority ceiling protocol for accessing shared resources.
• Low latency–three clocks from receipt of interrupt request from peripheral to interrupt request to
processor.
10.1.4 Modes of Operation
The interrupt controller has two handshaking modes with the processor: software vector mode and
hardware vector mode. The state of the hardware vector enable bit, INTC_MCR[HVEN], determines
which mode is used.
In debug mode the interrupt controller operation is identical to its normal operation of software vector
mode or hardware vector mode.
10.1.4.1 Software Vector Mode
In software vector mode, there is a common interrupt exception handler address which is calculated by
hardware as shown in
Figure 10-5 . The upper half of the interrupt vector prefix register (IVPR) is added
to the offset contained in the external input interrupt vector offset register (IVOR4). Note that since bits
IVOR4[28:31] are not part of the offset value, the vector offset must be located on a quad-word (16-byte)
aligned location in memory.
In software vector mode, the interrupt exception handler software must read the INTC interrupt
acknowledge register (INTC_IACKR) to obtain the vector associated with the corresponding peripheral
or software interrupt request. The INTC_IACKR register contains a 32-bit address for a vector table base
address (VTBA) plus an offset to access the interrupt vector (INTVEC). The address is then used to branch
to the corresponding routine for that peripheral or software interrupt source.
1. The total number of available interrupts on this device is 332: 298 peripheral IRQs, eight software-configurable IRQs, and
16 reserved. Because the memory is mapped in four-byte words, the total number of interrupt vectors must be a multiple of four,
therefore additional interrupt vectors exist to complete the word. This results in a total of 332 interrupt vectors. However, interrupt
vectors 330–332 are reserved and not available.