NXP Semiconductors MPC5566, Reference Manual

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e200z6 Core Complex
MPC5566 Microcontroller Reference Manual, Rev. 2
3-24 Freescale Semiconductor
indicating the line contains valid data consistent with memory. Dirty cache lines have the D and V bits set,
indicating that the line has valid entries that have not been written to memory. In addition, a cache line can
be locked (L bit set) indicating the line is not available for replacement.
The cache must be invalidated after a hardware reset; a hardware reset does not invalidate the cache lines.
Following initial power-up, the cache contents are undefined. If the L, D, or V bits are set on any lines, the
software must invalidate cache before the cache is enabled.
Figure 3-15 illustrates the general flow of cache operation.
Figure 3-15. Cache Lookup Flow
31 27 26 20
19 0
Index Tag data / tag reference
MUX
Comparator
0
1
2
7
Logical OR
HIT 7
HIT 2
HIT 1
HIT 0
Hit
Select
Set 0
Set 1
Set 127
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•
•
Tag
Reference
A[0:19]
Way 0
Way 1
Way 2
Way 7
Data or
instruction
Status DW0 DW1 DW2 DW3
Tag
Status DW0 DW1 DW2 DW3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Virtual address
Set
Select
A[20:26]
Tag
Physical address
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•