NXP Semiconductors MPC5566, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
9-40 Freescale Semiconductor
4. Write the 32-byte TCD for each channel that can request service.
5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers.
6. Request channel service by either software (setting the TCD.START bit) or by hardware (slave
device asserting its eDMA peripheral request signal).
After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The eDMA engine reads the entire TCD, including the
primary transfer control parameter shown in
Table 9-22 , for the selected channel into its internal address
path module. As the TCD is being read, the first transfer is initiated on the system bus unless a
configuration error is detected. Transfers from the source (as defined by the source address, TCD.SADDR)
to the destination (as defined by the destination address, TCD.DADDR) continue until the specified
number of bytes (TCD.NBYTES) have been transferred. When the transfer is complete, the eDMA
engine's local TCD.SADDR, TCD.DADDR, and TCD.CITER are written back to the main TCD memory
and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post
processing is executed: for example, interrupts, major loop channel linking, and scatter/gather operations,
if enabled.
Figure 9-27 shows how each DMA request initiates one minor loop transfer (iteration) without CPU
intervention. DMA arbitration can occur after each minor loop, and one level of minor loop DMA
preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration
count (biter).
Table 9-22. TCD Primary Control and Status Fields
TCD Field
Name
Description
START Control bit to explicitly start channel when using a software
initiated DMA service (Automatically cleared by hardware)
ACTIVE Status bit indicating the channel is currently in execution
DONE Status bit indicating major loop completion (Cleared by software
when using a software initiated DMA service)
D_REQ Control bit to disable DMA request at end of major loop
completion when using a hardware-initiated DMA service
BWC Control bits for “throttling” bandwidth control of a channel
E_SG Control bit to enable scatter-gather feature
INT_HALF Control bit to enable interrupt when major loop is half complete
INT_MAJ Control bit to enable interrupt when major loop completes