NXP Semiconductors MPC5566, Reference Manual

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Enhanced Time Processing Unit (eTPU)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 18-21
Table 18-7. ETPU_CDCR Field Descriptions
Field Description
0
STS
Start. Set by the host to start the data transfer between the parameter buffer pointed by PBBASE and the target
addresses selected by the concatenation of fields CTBASE and PARM0/1. The host receives wait-states until the
data transfer is complete. Coherency logic resets STS after the data transfer is complete. For more information, refer
to the
eTPU Reference Manual .
0 (Write) does not start a coherent transfer.
1 (Write) starts a coherent transfer.
1–5
CTBASE
[0:4]
Channel transfer base. This field concatenates with fields PARM0/PARM1 to determine the absolute offset (from the
SDM base) of the parameters to be transferred:
Parameter 0 address = {CTBASE, PARM0}
×
4 + SDM base
Parameter 1 address = {CTBASE, PARM1}
×
4 + SDM base
6–15
PBBASE
[0:9]
Parameter buffer base address. Points to the base address of the parameter buffer location, with granularity of 2
parameters (8 bytes). The host (byte) address of the first parameter in the buffer is PBBASE
×
8 + SDM Base
Address.
16
PWIDTH
Parameter width selection. Selects the width of the parameters to be transferred between the PB and the target
address.
0 Transfer 24-bit parameters. The upper byte remains unchanged in the destination address.
1 Transfer 32-bit parameters. All 32 bits of the parameters are written in the destination address.
17–23
PARM0
[0:6]
Channel parameter number 0. This field in concatenation with CTBASE[3:0] determine the address offset (from the
SDM base address) of the parameter which is the destination or source (defined by WR) of the coherent transfer.
The SDM address offset of the parameter is {CTBASE, PARM0}*4. PARM0 allows non-contiguous parameters to be
transferred coherently
1
.
1
The parameter pointed by {CTBASE, PARM0} is the first transferred.
24
WR
Read/Write selection. This bit selects the direction of the coherent data transfer.
0 Read operation. Data transfer is from the selected parameter RAM address to the PB.
1 Write operation. Data transfer is from the PB to the selected parameter RAM address.
25–31
PARM1
[0:6]
Channel parameter number 1. This field in concatenation with CTBASE[3:0] determines the address offset (from the
SDM base) of the parameter which is the destination or source (defined by WR) of the coherent transfer. The SDM
address offset of the parameter is {CTBASE, PARM1}*4. PARM1 allows non-contiguous parameters to be
transferred coherently
1
.