MPC5566 Microcontroller Reference Manual, Rev. 2
22-14
Freescale Semiconductor
19
LPB
Loop back. Configures FlexCAN2 to operate in loop-back mode. See
Section 22.1.4, “Modes of Operation
”
for information about this operating mode.
0 Loop back disabled
1 Loop back enabled
20
TWRNMSK
This bit provides a mask for the TX Warning Interrupt associated with the TWRNINT flag in the Error
and Status Register. This bit has no effect if the WRNEN bit in CAN
x
_MCR is negated and it is read as zero
when WRNEN is negated.
1 = Tx Warning Interrupt enabled
0 = Tx Warning Interrupt disabled
21
RWRNMSK
This bit provides a mask for the RX Warning Interrupt associated with the RWRNINT flag in the Error
and Status Register. This bit has no effect if the WRNEN bit in CAN
x
_MCR is negated and it is read as zero
when WRNEN is negated.
1 = Rx Warning Interrupt enabled
0 = Rx Warning Interrupt disabled
22–23
Reserved.
24
SMP
Sampling mode. Defines the sampling mode of each bit in the receiving messages (RX).
0 Just one sample is used to determine the RX bit value
1 Three samples are used to determine the value of the received bit: the regular one (sample point) and
two preceding samples, a majority rule is used
25
BOFFREC
Bus off recovery mode. Defines how FlexCAN2 recovers from bus off state. If this bit is negated, automatic
recovering from bus off state occurs according to the CAN Specification 2.0B. If the bit is asserted,
automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated
by the user. If the negation occurs before 128 sequences of 11 recessive bits are detected on the CAN bus,
then bus off recovery happens as if the BOFFREC bit had never been asserted. If the negation occurs after
128 sequences of 11 recessive bits are detected, then FlexCAN2 re-synchronizes to the bus by waiting for
11 recessive bits before joining the bus. After negation, the BOFFREC bit can be re-asserted again during
bus off, but it is only effective the next time the module enters bus off. If BOFFREC was negated when the
module entered bus off, asserting it during bus off is not effective for the current bus off recovery.
0 Automatic recovering from bus off state enabled, according to CAN Spec 2.0 part B
1 Automatic recovering from bus off state disabled
26
TSYN
Timer sync mode. Enables a mechanism that resets the free-running timer each time a message is
received in message buffer 0. This feature provides means to synchronize multiple FlexCAN2 stations with
a special SYNC message (that is, global network time).
0 Timer sync feature disabled
1 Timer sync feature enabled
Note:
There is a possibility of 4
–
5 ticks count skew between the different FlexCAN2 stations that would
operate in this mode.
27
LBUF
Lowest buffer transmitted first. This bit defines the ordering mechanism for message buffer transmission.
0 Buffer with lowest ID is transmitted first
1 Lowest number buffer is transmitted first
Table 22-8. CAN
x
_CR Field Descriptions
Bits
Description
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
