NXP Semiconductors MPC5566, Reference Manual

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Enhanced Direct Memory Access (eDMA)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 9-17
9.2.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR)
The EDMA_CIRQR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_IRQRH or EDMA_IRQRL to disable the interrupt request for a given channel. The given value
on a register write causes the corresponding bit in the EDMA_IRQRH or EDMA_IRQRL to be cleared.
Setting bit 1 (CINT
n ) provides a global clear function, forcing the entire contents of the EDMA_IRQRH
or EDMA_IRQRL to be zeroed, disabling all DMA interrupt requests. Reads of this register return all
zeroes.
9.2.2.10 eDMA Clear Error Register (EDMA_CER)
The EDMA_CER provides a simple memory-mapped mechanism to clear a given bit in the EDMA_ERH
or EDMA_ERL to disable the error condition flag for a given channel. The given value on a register write
causes the corresponding bit in the EDMA_ERH or EDMA_ERL to be cleared. Setting bit 1 (CERR
n )
provides a global clear function, forcing the entire contents of the EDMA_ERH and EDMA_ERL to be
zeroed, clearing all channel error indicators. Reads of this register return all zeroes.
Table 9-9. EDMA_CEEIR Field Descriptions
Field Description
0 Reserved
1–7
CEEI[0:6]
Clear enable error interrupt.
0–63 Clear corresponding bit in EDMA_EEIRH or EDMA_EEIRL
64–127 Clear all bits in EDMA_EEIRH or EDMA_EEIRL
Address: Base + 0x001C Access: User W/O
0 1 2 3 4 5 6 7
R 0 0 0 0 0 0 0 0
W CINT[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 9-12. eDMA Clear Interrupt Request (EDMA_CIRQR)
Table 9-10. EDMA_CIRQR Field Descriptions
Field Description
0 Reserved
1–7
CINT[0:6]
Clear interrupt request.
0–63 Clear corresponding bit in EDMA_IRQRH or EDMA_IRQRL
64–127 Clear all bits in EDMA_IRQRH or EDMA_IRQRL