NXP Semiconductors MPC5566, Reference Manual

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Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 1-19
module is communicated in serial format. The JTAGC module is compliant with the IEEE
®
1149.1-2001
standard.
1.5.21 Fast Ethernet Controller (FEC)
The MPC5566 fast Ethernet controller includes these distinctive features:
• IEEE 802.3 MAC (compliant with IEEE 802.3 1998 edition)
• Fully software compatible to the FEC module of Freescale's industry standard PowerQUICC
communications controller
• MII management interface for control and status
• Built-in FIFO and DMA controller
• Support for different Ethernet physical interfaces:
— IEEE 802.3 MII
— 10 Mbps 7-wire interface (industry standard)
• Support for full-duplex operation (200 Mbps throughput) with a system clock of 100 MHz.
• Support for half-duplex operation (100 Mbps throughput) with a system clock of 50 MHz.
• IEEE 802.3 full duplex flow control
• Programmable max frame length supports IEEE 802.1 VLAN tags and priority
• Retransmission from transmit FIFO following a collision (no system bus utilization)
• Automatic internal flushing of the receive FIFO for runts (collision fragments) and address
recognition rejects (no system bus utilization)
• Address recognition
— Frames with broadcast address may be always accepted or always rejected
— Exact match for single 48-bit individual (unicast) address
— Hash (64-bit hash) check of individual (unicast) addresses
— Hash (64-bit hash) check of group (multicast) addresses
— Promiscuous mode
• RMON and IEEE statistics
• Interrupts for network activity and error conditions