NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-28 Freescale Semiconductor
20.3.2.10 DSPI DSI Configuration Register (DSPI x _DSICR)
The DSPI x _DSICR selects attributes for DSI and CSI configurations. Do not write to the DSPI x _DSICR
while the DSPI is running.
The following table describes the fields in the DSPI deserial serial interface configuration register:
Address: Base + 0x00BC Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
MTOE
0
MTOCNT
0 0 0 0
TXSS TPOL TRRE CID
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R DCO
NT
DSICTAS
0 0 0 0
0 0
DPCS
5
DPCS
4
DPCS
3
DPCS
2
DPCS
1
DPCS
0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-12. DSPI DSI Configuration Register (DSPI x _DSICR)
Table 20-12. DSPI x _DSICR Field Descriptions
Field Description
0
MTOE
Multiple transfer operation enable. Enables multiple DSPIs connected in a parallel or serial configuration.
See
Section 20.4.4.7, “Multiple Transfer Operation (MTO) ,” for more information.
0 Multiple transfer operation disabled
1 Multiple transfer operation enabled
1 Reserved
2–7
MTOCNT
[0:5]
Multiple transfer operation count. Selects number of bits to be shifted out during a transfer in multiple transfer
operation. The field sets the number of SCK cycles that the bus master needs to generate to complete the
transfer. The number of SCK cycles used are one more than the value in the MTOCNT field. The number of SCK
cycles defined by MTOCNT must be equal to or greater than the frame size.
8–11 Reserved
12
TXSS
Transmit data source select. Selects the source of data to be serialized. The source can be data from host
software written to the DSPI DSI alternate serialization data register (DSPI
x _ASDR), or parallel output pin states
latched into the DSPI DSI serialization data register (DSPI x _SDR).
0 Source of serialized data is the DSPI x _SDR
1 Source of serialized data is the DSPI x _ASDR
13
TPOL
Trigger polarity. Selects the active edge of the internal hardware trigger input signal ( ht ). The bit selects which
edge initiates a transfer in the DSI configuration. See Section 20.4.4.5, “DSI Transfer Initiation Control ,” for more
information.
0 Falling-edge initiates a transfer
1 Rising-edge initiates a transfer