MPC5566 Microcontroller Reference Manual, Rev. 2
22-4
Freescale Semiconductor
22.1.4
Modes of Operation
The device supports four FlexCAN functional modes: normal, freeze, listen-only and loop-back. One low
power mode, module disabled, is supported.
22.1.4.1
Normal Mode
In normal mode, the module operates receiving and/or transmitting message frames, errors are handled
normally and all the CAN protocol functions are enabled. In this device, there is no distinction between
user and supervisor modes.
22.1.4.2
Freeze Mode
Freeze mode is entered when the FRZ bit in the module configuration register (CAN
x
_MCR) is asserted
while the HALT bit in the CAN
x
_MCR is set or debug mode is requested by the NPC. In freeze mode no
transmission or reception of frames is done, and synchronization with the CAN bus is lost. See
Section 22.4.6.1, “Freeze Mode
,” for more information.
22.1.4.3
Listen-Only Mode
The module enters this mode when the LOM bit in the CAN
x
_CR is asserted. In this mode, FlexCAN
operates in a CAN error passive mode, freezing all error counters and receiving messages without sending
acknowledgments.
22.1.4.4
Loop-Back Mode
The module enters this mode when the LPB bit in the CAN
x
_CR is asserted. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream output of the
transmitter is internally fed back to the receiver input. The CAN receive input pin (CNRX
x
) is ignored and
the transmit output (CNTX
x
) goes to the recessive state (logic 1). FlexCAN behaves as it normally does
when transmitting, and treats its own transmitted message as a message received from a remote node. In
this mode, FlexCAN ignores the bit sent during the ACK slot in the CAN frame acknowledge field to
ensure proper reception of its own message. Both transmit and receive interrupts are generated.
22.1.4.5
Module Disabled Mode
This low power mode is entered when the MDIS bit in the CAN_MCR is asserted. When disabled, the
module shuts down the clocks to the CAN protocol interface and message buffer management submodules.
Exit from this mode is done by negating the CAN_MCR[MDIS] bit. See
,” for more information.
Summary of Contents for MPC5566
Page 81: ...Introduction MPC5566 Microcontroller Reference Manual Rev 2 1 24 Freescale Semiconductor...
Page 135: ...Signal Description MPC5566 Microcontroller Reference Manual Rev 2 2 54 Freescale Semiconductor...
Page 189: ...Reset MPC5566 Microcontroller Reference Manual Rev 2 4 20 Freescale Semiconductor...
Page 603: ...Flash Memory MPC5566 Microcontroller Reference Manual Rev 2 13 38 Freescale Semiconductor...
Page 609: ...SRAM MPC5566 Microcontroller Reference Manual Rev 2 14 6 Freescale Semiconductor...
Page 1073: ...MPC5566 Microcontroller Reference Manual Rev 2 22 36 Freescale Semiconductor...
Page 1185: ...Nexus MPC5566 Microcontroller Reference Manual Rev 2 25 92 Freescale Semiconductor...
