NXP Semiconductors MPC5566, Reference Manual

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Interrupt Controller (INTC)
MPC5566 Microcontroller Reference Manual, Rev. 2
10-2 Freescale Semiconductor
10.1.2 Overview
Interrupt functionality for the device is handled between the e200z6 core and the interrupt controller. The
CPU core has 19 exception sources, each of which can interrupt the core. One exception source is from
the interrupt controller (INTC). The INTC provides priority-based preemptive scheduling of interrupt
requests. This scheduling scheme is suitable for statically scheduled hard real-time systems. The INTC is
optimized for a large number of interrupt requests. It is targeted to work with a PowerPC book E processor
and automotive powertrain applications where the ISRs nest to multiple levels.
Table 10-1 displays the interrupt sources and the number of interrupts available for each module;
Figure 10-2 shows a general diagram of INTC software vector mode.
Table 10-1. Interrupt Sources Available
Interrupt Source (IRQs)
Number of
Interrupts Available
Software 8
Watchdog 1
Memory 1
eDMA 66
FMPLL 2
External IRQ input pins 6
eMIOS 24
eTPU engine A 33
eTPU engine B 32
eQADC 31
DSPI 20
eSCI 2
FlexCAN 80
FEC 3