NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-54 Freescale Semiconductor
20.4.6.3 After SCK Delay (t
ASC
)
The after SCK x delay is the length of time between the last edge of SCK x and the negation of PCS x . See
Figure 20-34 and Figure 20-35 for illustrations of the after SCK x delay. The PASC and ASC fields in the
DSPI x _CTAR n registers select the after SCK delay. The relationship between these variables is given in
the following formula:
Table 20-25 shows an example of the computed after SCK delay.
20.4.6.4 Delay after Transfer (t
DT
)
The delay-after-transfer field is the amount of time between negation of the PCS x signal for a frame and
the assertion of the PCS x signal for the next frame. The PDT and DT fields in the DSPI x _CTAR n registers
select the delay after transfer.
See Figure 20-34 for an illustration of the delay after transfer. The following formula expresses the PDT
and DT delay-after-transfer relationship:
Table 20-26 shows an example of the computed delay after transfer.
20.4.6.5 Peripheral Chip Select Strobe Enable (PCSS)
The PCSS signal provides a delay to allow the PCS x signals to settle after transitioning thereby avoiding
glitches. When the DSPI is in master mode and PCSSE bit is set in the DSPI x _MCR, PCSS provides a
signal for an external demultiplexer to decode the PCS x [0:4] signals into as many as 32 glitch-free PCS x
signals.
Table 20-25. After SCK Delay Computation Example
PASC
Prescaler
Value
ASC
Scaler
Value
f
SYS
After SCK Delay
0b01 3 0b0100 32 100 MHz 0.96
μ
s
Table 20-26. Delay after Transfer Computation Example
PDT
Prescaler
Value
DT
Scaler
Value
f
SYS
Delay after Transfer
0b01 3 0b1110 32768 100 MHz 0.98 ms
t
ASC
=
f
SYS
ASC
×
PASC
1
×
t
DT
=
f
SYS
DT
×
PDT
1
×