NXP Semiconductors MPC5566, Reference Manual

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Deserial Serial Peripheral Interface (DSPI)
MPC5566 Microcontroller Reference Manual, Rev. 2
20-30 Freescale Semiconductor
20.3.2.11 DSPI DSI Serialization Data Register (DSPI x _SDR)
The DSPI x _SDR contains the signal states of the parallel input signals from the eTPU or the eMIOS. The
pin states of the parallel input signals are latched into the DSPI x _SDR on the rising edge of every system
clock. The DSPI x _SDR is read-only. When the TXSS bit in the DSPI x _DSICR is negated, the data in the
DSPI x _SDR is the source of the serialized data.
The following table describes the field in the DSPI deserial serial interface serialization data register:
Address: Base + 0x00C0 Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R SER_DATA [15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-13. DSPI DSI Serialization Data Register (DSPI x _SDR)
Table 20-13. DSPI x _SDR Field Description
Bits Description
0–15 Reserved
16–31
SER_
DATA
[15:0]
Serialized data. The SER_DATA field contains the signal states of the parallel input signals. SER_DATA [15:0] maps
to DSPI serialization inputs IN[15:0]. See
Section 20.4.4.6, “DSPI Connections to eTPUA, eTPUB, eMIOS and SIU .”