NXP Semiconductors MPC5566, Reference Manual

Page: 69 / 1268

Introduction
MPC5566 Microcontroller Reference Manual, Rev. 2
1-12 Freescale Semiconductor
1.5 Detailed Features
The following sections provide detailed information about each of the on-chip modules.
1.5.1 e200z6 Core Overview
The device uses the e200z6 core explained in detail in the e200z6 PowerPC
TM
Core Reference Manual .
The e200z6 CPU uses a seven-stage pipeline for instruction execution:
• Instruction fetch 1
• Instruction fetch 2
• Instruction decode and register file read
Enhanced Time Processing Unit (eTPU) 64 channels 64 channels
eTPU A Y Y
eTPU B Y Y
Code memory (KB) 16 20
Parameter RAM (KB) 3 4
Nexus Class 3 Class 3
Interrupt controller (INT) 308 329
7
Enhanced queued analog-to-digital converter (eQADC) 40 channel 40 channel
ADC 0 Y Y
ADC 1 Y Y
Fast Ethernet controller (FEC) — Y
8
FlexRay — —
FlexRay Nexus — —
Frequency modulated phase lock loop (FMPLL) Y Y
Maximum system frequency
9
132 MHz 147 MHz
Crystal range 8–20 MHz 8–20 MHz
Voltage regulator controller (VRC) Y Y
1
8-way associative
2
4-way and 8-way associative
3
32-byte flash page size for programming
4
Not externally available in all package configurations
5
Either ADDR[8:31] or ADDR[6:29] can be selected to have a 24-bit bus.
6
Updated FlexCAN module with optional individual receive filters
7
Although this device has a maximum of
329
interrupts, the logic requires that the total number of interrupts
be divisible by four. Therefore, the total number of interrupts specified for this device is 332.
8
The FEC signals are muxed with data bus pins DATA[16:31].
9
Initial automotive temperature range qualification.
Table 1-1. MPC5554 and MPC5566 Comparison (continued)
Module MPC5554 MPC5566