NXP Semiconductors MPC5566, Reference Manual

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Fast Ethernet Controller (FEC)
MPC5566 Microcontroller Reference Manual, Rev. 2
Freescale Semiconductor 15-19
Table 15-12 describes the fields and functions in the MIB block control register (MIBC):
15.3.4.2.9 Receive Control Register (RCR)
The RCR is programmed by the application. The RCR controls the operational mode of the receive block
and must be written only when ECR[ETHER_EN] = 0 (initialization time).
Address: Base + 0x0064 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R MIB_
DIS
ABLE
MIB_
IDLE
0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 15-10. MIB Control Register (MIBC)
Table 15-12. MIBC Field Descriptions
Field Description
0
MIB_DISABLE
A read/write control bit. If set, the MIB logic halts and does not update any MIB counters.
1
MIB_IDLE
A read-only status bit. If set the MIB block is not currently updating any MIB counters.
2–31 Reserved
Address: Base + 0x0084 Access: User R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0
MAX_FL
W
Reset 0 0 0 0 0 1 0 1 1 1 1 0 1 1 1 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0 0
FCE
BC_
REJ
PROM
MII_
MODE
DRT LOOP
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Figure 15-11. Receive Control Register (RCR)